Encoding:

Format:

MUL[_S].PH 

MUL.PH    rd, rs, rt

MUL_S.PH  rd, rs, rt

Purpose:

Multiply Vector Integer HalfWords to Same Size Products

Multiply two vector halfword values.

Description:

rd = (rs31..16 * rt31..16) || (rs15..0 * rt15..0)

Each of the two integer halfword elements in register rs is multiplied by the corresponding integer halfword element in register rt to create a 32-bit signed integer intermediate result.

In the non-saturation version of the instruction, the 16 least-significant bits of each 32-bit intermediate result are written to the corresponding vector element in destination register rd.

In the saturating version of the instruction, intermediate results that cannot be represented i n 16 bits are clipped to either the m aximum positive 16-bit value (0x7FFF hex adecimal) or the mi nimum negative 16-bit value (0x8000 hexadecimal), depending on the sign of the intermediate result. The saturated results are then written to the destination register.

To stay compliant with the base architecture, this instruction leaves the base HI/LO pair (accumulator ac0) UNPREDICTABLE after the operation completes. The other DSP Module accumulators, ac1, ac2, and ac3, are unchanged.

In the saturating instruction variant, if either multiplication results in an overflow or underflow, the instruction writes a 1 to bit 21 in the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

MUL.PH:
   tempB31..0 = MultiplyI16I16( GPR[rs]31..16, GPR[rt]31..16 )
   tempA31..0 = MultiplyI16I16( GPR[rs]15..0, GPR[rt]15..0 )
   GPR[rd]..0 = tempB15..0 || tempA15..0 
   HI..0 = UNPREDICTABLE
   LO..0 = UNPREDICTABLE
MUL_S.PH:
   tempB31..0 = sat16MultiplyI16I16( GPR[rs]31..16, GPR[rt]31..16 )
   tempA31..0 = sat16MultiplyI16I16( GPR[rs]15..0, GPR[rt]15..0 )
   GPR[rd]..0 = tempB15..0 || tempA15..0 
   HI..0 = UNPREDICTABLE
   LO..0 = UNPREDICTABLE
function MultiplyI16I16( a15..0, b15..0 ) 
   temp31..0 = a15..0 * b15..0
   if ( temp31..0 > 0x7FFF ) or ( temp31..0 < 0xFFFF8000 ) then
         DSPControlouflag:21 = 1
   endif
   return temp15..0
endfucntion MultiplyI16I16
function satMultiplyI16I16( a15..0, b15..0 ) 
   temp31..0 = a15..0 * b15..0
   if ( temp31..0 > 0x7FFF ) then
      temp31..0 = 0x00007FFF
      DSPControlouflag:21 = 1
   else
      if ( temp31..0 < 0xFFFF8000 ) then
         temp31..0 = 0xFFFF8000
          DSPControlouflag:21 = 1
      endif
   endif
   return temp15..0
endfucntion satMultiplyI16I16

Exceptions:

Reserved Instruction, DSP Disabled

Programming Notes:

The base MIPS64 architecture states that upon the after a GPR-targeting multiply instruction such as MUL, the contents of HI and LO are UNPREDICTABLE. To stay compliant with the base architecture, this multiply instruction states the same requirement. But this requirement does not apply to the new accumulators ac1-ac3 and hence a programmer must save the value in ac0 (which is the same as HI and LO) across a GPR-targeting multiply instruction, it needed, while the values in ac1-ac3 do not need to be saved.